Heat generation in silicon nanometric semiconductor devices

In nano-devices the presence of very high and rapidly varying electric fields is the cause of thermal heating of the carriers and the crystal lattice. In fact, the external electric field transfers energy to the electrons and in turn to the lattice through the scattering mechanism. This self-heating process can influence significantly the electrical behaviour because the dissipated electrical energy causes a temperature rise in the device resulting in increased power dissipation. Power dissipation limits the performance of electronics from handheld devices (≃ 103 W) to massive data centers (≃ 109 W), all primarily based on silicon micro/nanotechnology [2]. In a diffusion-like regime, where the charge carriers are in thermal equilibrium with the lattice, there are small temperature gradients, and the device length is much larger than the phonon mean free path, the electro-thermal transport can be described accurately using the non isothermal drift-diffusion model [9]. Here the classical drift-diffusion equations are coupled with the Fourier law via the heat generation rate term HD = J ·E+(R−G)(EG +3kBT ) (1)